In VLSI circuit design, electrical circuit analysis and simulation are important in predicting overall system yield and performance, through accurate and fast timing, power, and noise evaluation. As an example, timing analysis depends on a careful analysis of RC parasitics that are extracted from the physical design layout. Meanwhile, feature size is shrinking with every new process generation; therefore, there are multiple challenges never experienced by the semiconductor design community before. One problem is due to the dramatic increase in the amount of parasitics extracted from the physical design layout, which makes electrical analysis and especially simulation run slow or even be impossible to run.
Techniques have been proposed for reducing the extracted parasitics to allow the timing and simulation to run faster. FIG. 1 shows a general flow for parasitics reduction, in which parasitics are extracted 104 from a physical design layout 102, and then reduced 106. Finally, analysis or simulation 108 is performed.
Unfortunately, some parasitics reduction techniques are not realizable. That is, the reduction may preserve the electrical properties at the ports, but is not realizable as an RC network. Other parasitics reduction techniques are realizable. However, the realizable reduction technique itself may be very computationally intensive. Moreover, the realizable reduction technique may only work on limited circuit topologies. Thus, the benefit of reducing the parasitics is curtailed.
FIG. 2 shows a general flow for parasitics reduction in which a parasitics netlist is constructed 202 from a circuit design, then nodes and devices that cannot be eliminated from the parasitics netlist are marked 204. After identifying nodes for elimination 206, the identified nodes and their associated devices are eliminated 208. However, eliminating a node may require adding devices such that the electrical properties of RC network are preserved, which can lead to increasing the number of devices in the parasitics netlist. Some parasitics reduction techniques may have a criterion of not significantly increasing the number of devices when eliminating a node. The need to increase the number of devices when eliminating a node depends on the circuit topology. Thus, some parasitics reduction techniques only work well for limited types of circuit topologies.
In order to determine whether some parasitics reduction techniques may be applied, it may be necessary to identify the circuit topologies that are suitable for parasitics reduction. However, identifying the suitable topologies is itself a problem having superlinear complexity. Because of this, the benefit of parasitics reduction may be limited by the heavy cost of identifying suitable topologies for reduction.
The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section.